Digital Computing: Canonical Domain Analysis

Status: Canonical reference. Full 12-step analysis of digital computing as the substrate below the entity system. Position in the topology: The realization substrate for the entity system. Connected downward to physical hardware through realization edge, upward to entity system through bridge {Enc,Hsh,Prt,Prs,Sch,Net}.

Step 1 — Information Gathering

1.1 What we're analyzing

Digital computing — the domain of computational machinery that all software runs on. Not any specific computer or architecture, but the structural space of what digital computation IS. What every computer, from a microcontroller to a supercomputer to a phone, has in common.

1.2 Sources

• Computer architecture literature (Patterson & Hennessy, Hennessy & Patterson)
• Operating systems (Tanenbaum, Silberschatz)
• Networking (Kurose & Ross, Stevens)
• Historical: von Neumann architecture (1945), Turing machine (1936), stored program concept
• Real systems: x86, ARM, RISC-V, GPU, FPGA, microcontrollers, mainframes, cloud instances

1.3 The landscape

Step 2 — Landscape Analysis

2.1 What recurs across ALL digital computing systems

Every digital computer, regardless of architecture:

1. Stores binary data — bits in registers, memory, storage
2. Executes instructions — fetch-decode-execute or equivalent processing cycle
3. Has addressable memory — locations where data can be read and written
4. Has a processing clock — timing mechanism that sequences operations
5. Communicates with external devices — I/O of some form
6. Manages concurrent operations — even single-core systems interleave via interrupts

2.2 What varies

• Word size (8-bit to 64-bit+)
• Memory architecture (von Neumann vs Harvard, flat vs segmented vs virtual)
• Instruction set (CISC vs RISC vs VLIW vs GPU vs custom)
• Parallelism (single core, multi-core, SIMD, GPU, distributed)
• I/O model (programmed I/O, DMA, memory-mapped, message passing)
• Persistence (volatile RAM vs non-volatile storage vs in-memory)

Step 3/3b — Primitives and Partial Levels

3.1 Six primitives

3.2 Stability under 3/3b iteration

Splitting candidates:

• Memory (Mm) into Volatile + Persistent? Registers/RAM vs disk/SSD. These have fundamentally different latency and persistence properties. BUT: from the computing perspective, both are addressable storage — the difference is partial levels (speed, volatility, capacity), not separate primitives. Modern memory hierarchies blur the boundary (NVM, persistent memory, swap). Keep as one primitive with rich partial levels.
• Channel (Ch) into Input + Output? Most I/O is bidirectional at the hardware level. And the concept is "communication pathway" which is one structural concern regardless of direction. Keep as one.

Collapsing candidates:

• Instruction + Cycle? Instructions need cycles to execute, but instructions describe WHAT to do while cycles describe WHEN/HOW FAST. Independently variable — you can change the clock speed without changing the instruction set, or change the ISA without changing the clock. Keep separate.

6 primitives stable.

3.3 Partial levels

Word (Wd):

Phase transition: Wd2→Wd3 (Machine word). Below: operations on individual bytes. Above: native word operations (32/64-bit arithmetic, pointer-width addressing). Defines the machine's natural data width.

Memory (Mm):

Phase transition: Mm2→Mm3 (Cache hierarchy). Below: all memory accesses equal cost. Above: memory has LOCALITY — access patterns matter, spatial/temporal locality rewarded. Fundamentally changes how programs perform.

Phase transition: Mm3→Mm4 (Virtual memory). Below: programs see physical addresses. Above: programs see VIRTUAL addresses — isolation, protection, overcommit. Enables multi-process systems.

Instruction (In):

Phase transition: In0→In2 (Stored program). THE foundational transition. Below: the computer does one fixed thing. Above: the computer can do ANYTHING — it's programmable. The stored program concept (von Neumann, 1945) is digital computing's genesis transition.

Cycle (Cy):

Phase transition: Cy1→Cy2 (Pipelining). Below: one instruction completes per clock cycle. Above: multiple instructions overlap — throughput increases without faster clock. The beginning of instruction-level parallelism.

Channel (Ch):

Phase transition: Ch2→Ch3 (DMA). Below: CPU mediates ALL data transfer — bottleneck. Above: devices move data directly — CPU freed for computation. Enables high-throughput I/O.

Phase transition: Ch3→Ch4 (Network). Below: single-machine I/O. Above: multi-machine communication. The transition to distributed computing.

Process (Pr):

Phase transition: Pr1→Pr2 (Multi-process). Below: one program owns the machine. Above: multiple programs coexist safely. This enables multi-user systems and modern operating systems.

Phase transition: Pr3→Pr4 (Virtualization). Below: processes share one OS. Above: multiple OS instances on one machine. Enables cloud computing, elastic infrastructure.

Step 4 — Dependencies

Wd → (nothing; foundation — data must exist)
Mm → Wd (memory stores words)
In → Wd, Mm (instructions operate on words in memory)
Cy → In (cycles sequence instruction execution)
Ch → Wd, Mm (channels transfer words to/from memory)
Pr → In, Mm (processes are instruction sequences with memory state)

DAG:

Wd (hub)
  ├── Mm → In → Cy
  │         ↑
  │    Mm → Pr
  │         ↑
  └── Ch    In

More precisely:

Wd (hub — no dependencies)
  ├── Mm (stores words)
  │     ├── In (instructions operate on words in memory)
  │     │     ├── Cy (cycles sequence instructions)
  │     │     └── Pr (processes are instruction sequences — needs In + Mm)
  │     └── Ch (channels transfer words to/from memory)
  └── (Mm needs Wd; In needs Wd+Mm; Ch needs Wd+Mm; Pr needs In+Mm; Cy needs In)

Hub: Word (Wd). Everything operates on binary data.

Depth: Maximum chain: Wd → Mm → In → Cy (depth 3) or Wd → Mm → In → Pr (depth 3).

Step 5-6 — Pairs and Load Classification

C(6,2) = 15 pairs.

Heavy pairs

Medium pairs

Light pairs

7 heavy of 15 (47%). Moderate — appropriate for a well-structured computing substrate.

Step 7 — Coherent Sub-lattice

Dependencies

Wd is hub. Mm→Wd. In→Wd+Mm. Cy→In. Ch→Wd+Mm. Pr→In+Mm.

Valid subsets of {Mm, In, Cy, Ch, Pr} given Wd:

• In requires Mm
• Cy requires In (which requires Mm)
• Ch requires Mm
• Pr requires In+Mm (In requires Mm, so Pr requires Mm+In)

Enumerate:

Valid: {}, {Mm}, {Mm,Ch}, {Mm,In}, {Mm,In,Cy}, {Mm,In,Ch}, {Mm,In,Pr}, {Mm,In,Cy,Ch}, {Mm,In,Cy,Pr}, {Mm,In,Ch,Pr}, {Mm,In,Cy,Ch,Pr} = 11.

Including {} and {Wd}: {} is 1, the 11 above each include Wd.

Total: 1 + 11 = 12 coherent subsets of 64.

Filter: 12/64 = 18.75%. Tight — the dependency chain Wd→Mm→In→{Cy,Pr} creates strong filtering. Comparable to entity system (14%) and biology (12.5%).

Step 8 — Hasse Walks (Build-up Paths)

Path α — The historical path (how computing actually developed)

{} → {Wd} → {Wd,Mm} → {Wd,Mm,In} → {Wd,Mm,In,Cy} → {Wd,Mm,In,Cy,Ch} → Full

Data → memory → stored program → clocked execution → I/O → processes.

This IS roughly the historical order: binary representation (1930s-40s) → memory (1940s) → stored program (von Neumann 1945) → clocked execution (practical computers) → I/O (peripherals) → multi-process (time-sharing 1960s).

Path β — I/O before clock

{} → {Wd} → {Wd,Mm} → {Wd,Mm,Ch} → {Wd,Mm,In,Ch} → {Wd,Mm,In,Cy,Ch} → Full

Memory with I/O before stored program — like a DMA controller or I/O processor that moves data before computation is programmable. Rare historically but exists in some embedded systems.

Path γ — Process before clock

{} → {Wd} → {Wd,Mm} → {Wd,Mm,In} → {Wd,Mm,In,Pr} → {Wd,Mm,In,Pr,Ch} → Full

Multi-process before pipelining — like early time-sharing systems where process isolation came before instruction-level parallelism. This WAS the actual path for mainframes (multi-process in 1960s, pipelining in 1970s-80s).

Phase transitions along paths

In0→In2 (stored program) is the genesis transition — the moment computing becomes GENERAL-PURPOSE. Before: fixed-function machines. After: any computation expressible as a program.

Step 9 — Load-bearing Compositions

Core triad

{Wd, Mm, In} — Word, Memory, Instruction.

"What is a stored-program computer?" → Binary WORDS stored in MEMORY executed as INSTRUCTIONS. The von Neumann architecture in three primitives.

All three pairs heavy: Wd-Mm ✓, Mm-In ✓, Wd-In (medium — instructions encoded as words) — borderline.

This IS the minimal computer. Everything else (clock, I/O, processes) builds on this foundation.

Secondary triad

{Mm, In, Pr} — Memory, Instruction, Process.

"What is a multi-process computer?" → INSTRUCTIONS executing in MEMORY within isolated PROCESSES. The operating system core.

All three pairs heavy: Mm-In ✓, In-Pr ✓, Mm-Pr ✓.

Named compositions

Quad

{Wd, Mm, In, Pr} — The general-purpose multi-process computer. This is what every modern OS runs on — stored program with process isolation. Add Cy for performance, Ch for communication.

Higher / full set

{Wd, Mm, In, Cy, Ch, Pr} — Modern computer. The maximal substrate: general-purpose (stored program) + high-throughput (pipelined) + networked (channels) + virtualized (processes). Peaks at the most-complete manifestations (cloud instance, x86 server). Carried as an explicit higher composition for full-set coverage, consistent with the entity-system complete-substrate composition.

Step 10 — Emergent Properties

Step 11 — Cross-Domain Patterns

Comparison to entity system substrate

Both are substrates with tight filters and 6 primitives. The entity system is MORE integrated (73% heavy pairs vs 47%) because it was designed for all primitives to interact, while digital computing has more independent axes (clock and I/O are loosely coupled to other concerns).

How digital computing connects to entity system

The bridge primitives {Enc, Hsh, Prt, Prs, Sch, Net} translate between:

• Wd (binary words) ↔ E (typed entities) — via Encoding (Enc)
• Mm (memory addresses) ↔ I (content hashes) — via Hash (Hsh)
• Ch (network channels) ↔ P (peer connections) — via Network (Net)
• Pr (processes) ↔ X (handlers) — via Scheduler (Sch)
• Mm (persistent storage) ↔ T (tree state) — via Persistence (Prs)
• Ch (wire protocol) ↔ M (emit events) — via Protocol (Prt)

Step 12 — Manifestation Landscape

Positioned systems

What the landscape reveals

The Pr axis differentiates eras: ENIAC at Pr0 (bare metal), mainframes at Pr2 (multi-process), cloud at Pr-Full (distributed/elastic). Process isolation IS the arc of computing history.

GPUs are Pr-heavy, Mm-moderate: Thousands of threads with hierarchical memory. This is the OPPOSITE of traditional CPUs (moderate Pr, heavy Mm with virtual memory). Different computational models occupy different lattice positions.

Quantum computers are early across everything — Wd4 (qubits are novel) but Mm1, In2, Cy1, Ch1, Pr0. Analogous to the earliest classical computers. The landscape correctly positions quantum as embryonic.

AWS Lambda is Full on Ch and Pr — the cloud abstracts everything below. This IS what "serverless" means structurally: Ch-Full (network as programmable resource) + Pr-Full (processes as elastic, distributed units). The underlying Wd/Mm/In/Cy are abstracted away.

Summary

Referenced by the model

Cited as a source by 1 model record (browse the model census):

• digital-computing — domain entity/sc1