Physical Hardware: Canonical Domain Analysis

Status: Canonical reference. Full 12-step analysis of physical hardware — the substrate below digital computing. Position in the topology: Realization substrate for digital computing. Connected downward to physics/chemistry (semiconductor physics, electromagnetism) through realization edge, upward to digital computing through bridge.

Step 1 — Information Gathering

1.1 What we're analyzing

Physical hardware — the tangible machinery that digital computing runs on. Chips, circuits, memory cells, buses, power supplies, physical interfaces. Not the logical abstraction (digital computing) and not the physics (semiconductor physics, electromagnetism), but the ENGINEERED PHYSICAL LAYER in between.

1.2 Sources

Digital design (Weste & Harris, Rabaey)
Computer organization (Patterson & Hennessy — hardware chapters)
Semiconductor physics (Streetman & Banerjee — for bridge to physics)
PCB design, system integration, thermal management
Historical: vacuum tubes → transistors → ICs → VLSI → SoC

1.3 The landscape

System	Era	What it is
Vacuum tube computer (1940s)	First generation	Tubes as switches, relay memory, wired program
Transistor computer (1950s-60s)	Second generation	Discrete transistors, core memory, smaller/faster
Integrated circuit (1960s-70s)	Third generation	Multiple transistors on one chip, SSI→MSI→LSI
Microprocessor (1970s+)	Fourth generation	Entire CPU on one chip — Intel 4004, 8080, 8086
VLSI (1980s+)	Dense integration	Millions of transistors, complex SoCs
Modern SoC (2010s+)	System on chip	CPU+GPU+memory+I/O on one die
Chiplet/3D (2020s+)	Advanced packaging	Multiple dies in one package, 3D stacking

Step 2 — Landscape Analysis

2.1 What recurs across ALL physical hardware

Every computing device, from a vacuum tube machine to a modern SoC:

Switching elements that represent binary states — tubes, transistors, relays
Interconnections that carry signals between elements — wires, traces, buses
Storage elements that retain state — flip-flops, SRAM cells, DRAM cells, flash cells
Timing mechanisms that synchronize operations — oscillators, clock distribution
Power delivery that energizes everything — voltage regulation, power planes
Physical interfaces that connect to the outside world — pins, connectors, antennas, sensors

Step 3/3b — Primitives and Partial Levels

3.1 Six primitives

#	Primitive	What it is
1	Switch (Sw)	Binary state element — the fundamental computing component. Transistor, relay, vacuum tube, memristor.
2	Interconnect (Ic)	Signal pathway between elements — wire, trace, bus, optical link, wireless.
3	Storage (St)	State retention element — flip-flop, SRAM cell, DRAM cell, flash cell, magnetic domain.
4	Oscillator (Os)	Timing reference — crystal oscillator, PLL, clock distribution network.
5	Power (Pw)	Energy delivery system — voltage regulation, power planes, battery, harvesting.
6	Port (Pt)	Physical interface to external world — pin, connector, antenna, sensor, actuator.

3.2 Stability under 3/3b iteration

Splitting candidates:

Switch (Sw) into Logic + Amplification? Logic gates and analog amplifiers both use transistors but do different things. BUT: at the hardware level, both are transistor configurations — the difference is how they're connected, not what they ARE. Keep as one with partial levels.
Storage (St) into Volatile + Non-volatile? SRAM/DRAM vs Flash/MRAM. Different physics, different properties. BUT: both retain state — the difference is retention time (partial level), not structural role. Keep as one.
Port (Pt) into Input + Output? Most physical interfaces are bidirectional at the electrical level (GPIO pins, bidirectional buses). Keep as one.

Collapsing candidates:

Interconnect + Power? Both are "things running through the board." BUT: signal and power are structurally independent — you can have signal without adequate power (brownout) or power without signal (powered but idle). Different design concerns, different failure modes. Keep separate.

6 primitives stable.

3.3 Partial levels

Switch (Sw):

Level	Description	Instance
Sw0	No switches	Passive components only — resistors, capacitors
Sw1	Discrete switches	Individual relays, vacuum tubes, discrete transistors
Sw2	Integrated gates	Logic gates on a chip — AND, OR, NOT, NAND
Sw3	Complex logic blocks	ALU, multiplexer, decoder — functional units on chip
Sw4	Processor cores	Full CPU/GPU cores — billions of transistors as one functional unit
Full Sw	Reconfigurable logic	FPGA, reconfigurable computing — switches that can be reprogrammed

Phase transition: Sw1→Sw2 (Integration). Below: each switch is a separate physical component. Above: switches integrated on silicon — density, speed, and reliability jump by orders of magnitude. This is the integrated circuit revolution (1960s).

Phase transition: Sw3→Sw4 (Processor). Below: functional blocks that need external coordination. Above: self-contained processor — fetches, decodes, executes autonomously. The microprocessor revolution (1970s).

Interconnect (Ic):

Level	Description	Instance
Ic0	No interconnect	Isolated components
Ic1	Point-to-point wires	Individual wires connecting specific components
Ic2	Shared bus	Multiple components share a common bus — address/data/control
Ic3	Hierarchical buses	Multiple bus levels — on-chip, board-level, backplane
Ic4	Network-on-chip	Packet-switched interconnect within a chip or between chiplets
Full Ic	Optical/wireless interconnect	High-bandwidth, low-latency interconnect beyond electrical — photonic, RF

Phase transition: Ic1→Ic2 (Shared bus). Below: every connection is dedicated. Above: components share communication infrastructure — enables modular, expandable systems. The bus architecture (1960s-70s).

Phase transition: Ic3→Ic4 (Network-on-chip). Below: buses with fixed topology. Above: packet-switched networks within the chip — enables scalable multi-core/chiplet designs. Modern SoC architecture.

Storage (St):

Level	Description	Instance
St0	No storage	Combinational logic only — no state retention
St1	Flip-flops/latches	Single-bit state elements — registers, pipeline stages
St2	SRAM	Fast, volatile, on-chip — cache, register files
St3	DRAM	Dense, volatile, off-chip — main memory
St4	Non-volatile storage	Flash, SSD, magnetic disk — persistent across power cycles
Full St	Universal memory	Non-volatile, fast, dense — MRAM, ReRAM, persistent memory bridging volatile/non-volatile

Phase transition: St2→St3 (DRAM). Below: small, fast, on-chip memory. Above: large, separate memory chips — enables programs larger than cache. The memory hierarchy begins.

Phase transition: St3→St4 (Non-volatile). Below: state lost on power-off. Above: state PERSISTS across power cycles. Enables stored programs, databases, file systems — anything that survives rebooting.

Oscillator (Os):

Level	Description	Instance
Os0	No oscillator	Asynchronous or manually clocked
Os1	Fixed oscillator	Crystal oscillator — single fixed frequency
Os2	Clock distribution	Clock tree distributing timing across chip/board
Os3	PLL/frequency synthesis	Programmable frequency, clock multiplication/division
Os4	Multi-domain clocking	Different clock domains for different subsystems — async boundaries
Full Os	Dynamic frequency	DVFS (dynamic voltage and frequency scaling), power-aware clocking

Phase transition: Os1→Os2 (Clock distribution). Below: one oscillator drives nearby circuits. Above: clock signal distributed to ALL circuits with controlled skew — synchronous digital design at scale.

Power (Pw):

Level	Description	Instance
Pw0	No power management	Direct connection to supply — no regulation
Pw1	Regulated supply	Voltage regulators — stable power to components
Pw2	Multi-rail power	Different voltages for different subsystems (core, I/O, memory)
Pw3	Power gating	Ability to power down unused blocks — reduces idle power
Pw4	Dynamic power management	Runtime voltage/frequency adjustment based on workload
Full Pw	Energy harvesting	Self-powered — solar, thermal, kinetic energy harvesting

Phase transition: Pw2→Pw3 (Power gating). Below: everything powered all the time. Above: selective power-down — enables mobile computing (battery life) and data center efficiency.

Port (Pt):

Level	Description	Instance
Pt0	No external interface	Fully isolated chip
Pt1	Dedicated pins	Fixed-function I/O pins — power, ground, clock in/out
Pt2	General-purpose I/O	GPIO, configurable pins — can be input or output
Pt3	Standard interfaces	USB, Ethernet, PCIe, SPI, I2C — standardized protocols on physical connectors
Pt4	High-speed serial	Multi-gigabit serial links — PCIe Gen5, Thunderbolt, 100G Ethernet
Full Pt	Wireless/optical	Radio (WiFi, Bluetooth, 5G), optical (fiber), sensor arrays — no physical connector needed

Phase transition: Pt2→Pt3 (Standard interfaces). Below: custom pin assignments. Above: STANDARD connectors and protocols — any USB device works with any USB port. Interoperability at the physical level.

Step 4 — Dependencies

Sw → (nothing; foundation — switches are the basic computing element)
Ic → Sw (interconnect connects switches)
St → Sw (storage elements are made of switches — flip-flops from gates)
Os → Sw, Ic (oscillator drives switches through interconnect)
Pw → (nothing; independent — power exists independently of logic)
Pt → Ic (ports are interconnect endpoints to the outside world)

Two independent roots: Sw (Switch) and Pw (Power). Logic and energy are independently necessary — you need both but neither derives from the other.

DAG:

Sw (root 1)          Pw (root 2)
  ├── Ic → Pt
  ├── St
  └── Os

This mirrors the SSA's two-root structure (En + Cx) and app architecture's two-root structure (D + Pc). The pattern of an internal logic root plus an independent external/energy root recurs.

Depth: Maximum chain: Sw → Ic → Pt (depth 2). Shallow.

Step 5-6 — Pairs and Load Classification

C(6,2) = 15 pairs.

Heavy pairs

#	Pair	Content	Why heavy
1	Sw-Ic	Logic fabric	Switches connected by interconnect — THE hardware foundation. Gates + wires = digital circuits.
2	Sw-St	Stateful logic	Switches configured as storage — flip-flops, registers. Sequential circuits.
3	Sw-Os	Clocked logic	Switches synchronized by oscillator — synchronous digital design.
4	Ic-Pt	External connectivity	Interconnect reaching the outside world — all I/O goes through this.
5	Ic-St	Memory bus	Interconnect to storage — address/data buses to memory chips.
6	Sw-Pw	Powered switches	Switches need power to operate — switching power, leakage, thermal.
7	St-Os	Clocked storage	Storage elements synchronized by clock — register capture timing, memory refresh.

Medium pairs

Pair	Why medium
Ic-Os	Clock distribution IS an interconnect concern — but it's a specific kind.
Ic-Pw	Power distribution shares physical routing with signal — power planes, decoupling.
St-Pw	Storage power — DRAM refresh, flash write voltage. Real but specialized.
Pt-Pw	Port power — USB power delivery, PoE. Real but specialized.
Os-Pw	Clock and power interact — DVFS couples frequency to voltage. Real.

Light pairs

Pair	Why light
St-Pt	Storage and ports — indirect through interconnect.
Os-Pt	Clock and ports — ports have their own timing, loosely coupled to system clock.
Pt-Pw	Already listed as medium.

7 heavy of 15 (47%). Same as digital computing — moderate, well-structured substrate.

Step 7 — Coherent Sub-lattice

Dependency constraints

Two independent roots: Sw (logic) and Pw (energy). The remaining dependencies are Ic→Sw, St→Sw, Os→Sw∧Ic, Pt→Ic. Pw has no dependencies and is structurally independent of Sw (a power system is physically meaningful without logic, even if useless as computing hardware); we keep Pw independent, consistent with how other independent roots are treated.

Counting coherent subsets of 2^6 = 64

Pw is free (no dependencies), so it contributes a factor of 2. Count the valid configurations of {Sw, Ic, St, Os, Pt}, then double for Pw.

Sw absent. Ic→Sw forces Ic absent; then St→Sw forces St absent, Os→Ic forces Os absent, Pt→Ic forces Pt absent. Only the empty set. → 1.
Sw present, Ic absent. Os and Pt both require Ic, so both absent. St requires only Sw (present), so St is free. → {Sw}, {Sw,St} = 2.
Sw present, Ic present. St, Os, Pt are each independently free (Os needs Sw∧Ic ✓, Pt needs Ic ✓). → 2³ = 8.

Valid configurations of {Sw,Ic,St,Os,Pt}: 1 + 2 + 8 = 11. Doubling for the free Pw: 22 coherent subsets of 64.

(The empty set and {Pw} are the only coherent subsets without Sw — every other primitive transitively requires Sw.)

Filter: 22/64 = 34.4%. Moderate — looser than digital computing (18.75%) because the two-root structure (Sw + Pw independent) plus the shallow dependency depth (only Os and Pt have dependencies beyond the hub) creates more valid combinations. The hardware level is more modular than the computing level, whose deeper Wd→Mm→In→{Cy,Pr} chain filters harder.

Step 8 — Hasse Walks (Build-up Paths)

Path α — Historical (how hardware actually developed)

{} → {Sw} → {Sw,Ic} → {Sw,Ic,St} → {Sw,Ic,St,Os} → {Sw,Ic,St,Os,Pw} → Full

Switches → interconnected → with storage → clocked → powered properly → with external interfaces.

Roughly: vacuum tubes (Sw1) → wired circuits (Ic1) → flip-flop memory (St1) → crystal clock (Os1) → regulated power (Pw1) → I/O connectors (Pt2+).

Path β — Power-first (embedded/IoT perspective)

{} → {Pw} → {Sw,Pw} → {Sw,Ic,Pw} → {Sw,Ic,St,Pw} → {Sw,Ic,St,Os,Pw} → Full

Power system designed first (battery, harvesting), then logic added. Common in energy-constrained embedded design where power budget is the primary constraint.

Path γ — Interface-first (peripheral design)

{} → {Sw} → {Sw,Ic} → {Sw,Ic,Pt} → {Sw,Ic,St,Pt} → {Sw,Ic,St,Os,Pt} → Full

I/O interface designed first — a peripheral that connects to an existing system. Sensors, actuators, network interface cards. The external interface drives the design.

Phase transitions

Transition	What changes	Historical
Sw1→Sw2 (integration)	Switches on silicon — IC revolution	1960s
Sw3→Sw4 (processor)	Autonomous processor on chip — microprocessor	1971 (Intel 4004)
St2→St3 (DRAM)	Dense off-chip memory — memory hierarchy	1970 (Intel 1103)
St3→St4 (non-volatile)	Persistent storage — data survives power loss	Flash: 1980s
Ic3→Ic4 (NoC)	Network-on-chip — scalable multi-core	2000s+
Pw2→Pw3 (power gating)	Selective power-down — mobile computing	2000s+
Pt2→Pt3 (standard interfaces)	USB, Ethernet — interoperable I/O	1990s+

Step 9 — Load-bearing Compositions

Core triad

{Sw, Ic, St} — Switch, Interconnect, Storage.

"What is a digital circuit?" → SWITCHES connected by INTERCONNECT with STORAGE for state. The minimum sequential digital system.

All three pairs heavy: Sw-Ic ✓, Sw-St ✓, Ic-St ✓.

This maps directly to digital computing's core triad:

Sw (switches) realizes Wd (words) — switches represent binary values
Ic (interconnect) realizes Mm (memory addressing) — wires carry addresses and data
St (storage) realizes Mm (memory content) — storage cells hold data

Secondary triad

{Sw, Os, Pw} — Switch, Oscillator, Power.

"What does every switch need to operate?" → A CLOCK to synchronize it and POWER to energize it. The operational requirements.

Sw-Os ✓, Sw-Pw ✓, Os-Pw (medium — DVFS couples them). Borderline but structurally real.

Named compositions

Composition	Name	What it captures
{Sw, Ic, St}	Sequential circuit	Logic + interconnect + state = digital systems
{Sw, Ic, Pt}	I/O circuit	Logic + interconnect + external interface = peripheral
{Sw, Os, Pw}	Operating conditions	Timing + energy = what makes switches work
{Sw, Ic, St, Os}	Synchronous digital system	The standard digital design paradigm
{Ic, St, Pt}	Memory-mapped I/O	Storage and ports sharing address space
{Sw, Ic, St, Os, Pw}	System on chip	Complete computer on one die (Sw4+, St4+)
{Sw, Ic, St, Os, Pw, Pt}	Modern computing platform	Maximal substrate: processor + memory + I/O + power + networking

Quad

{Sw, Ic, St, Os} — The synchronous digital system. Clocked switches connected by wires with storage. This IS what every modern digital chip is — the standard design paradigm since the 1970s.

Higher / full set

{Sw, Ic, St, Os, Pw} (System on chip) and the full {Sw, Ic, St, Os, Pw, Pt} (Modern computing platform) are the maximal compositions. The full set adds standard external interfaces (Pt3+) to the SoC — processor + memory + I/O + power + networking integrated on one die; it should peak at the most-integrated SoC manifestations (e.g. Apple M3). Carried as explicit higher compositions for full-set coverage, consistent with the entity-system complete-substrate composition.

Step 10 — Emergent Properties

Composition	Regime	Emergent Property
{Sw}	Sw2+ (integrated)	Logic gates — Boolean operations on chip
{Sw, Ic}	Ic2+ (bus)	Digital circuits — combinational logic networks
{Sw, Ic, St}	St1+ (flip-flops)	Sequential circuits — state machines, counters, registers
{Sw, Ic, St, Os}	Os2+ (distributed clock)	Synchronous digital system — the standard design paradigm
{Sw, Ic, St, Os}	Sw4+ (processor)	Autonomous processor — fetch-decode-execute on chip
{Sw, Ic, Pt}	Pt3+ (standard interfaces)	Interoperable hardware — plug-and-play peripherals
{Sw, Pw}	Pw3+ (power gating)	Mobile computing — battery-operated with power management
{Sw, Ic, St, Os, Pw}	Sw4+, St4+	System on chip — complete computer on one die
Full set	All high	Modern computing platform — processor + memory + I/O + power + networking

Step 11 — Cross-Domain Patterns

Comparison to digital computing

Property	Physical hardware	Digital computing
Primitives	6	6
Filter	34.4%	18.75%
Heavy pairs	7/15 (47%)	7/15 (47%)
Core triad	{Sw, Ic, St}	{Wd, Mm, In}
Hub	Sw (switch)	Wd (word)
Independent roots	2 (Sw, Pw)	1 (Wd)
Genesis	Sw1→Sw2 (IC revolution)	In0→In2 (stored program)

Same pair density (47%). Hardware is looser filter (34.4% vs 18.75%) because of the two-root structure (Sw + Pw independent). Digital computing has a deeper dependency chain.

The bridge between hardware and digital computing

The bridge from physical hardware to digital computing translates:

Hardware primitive	Bridge mechanism	Computing primitive
Sw (switches)	Gate-level design, logic synthesis	Wd (binary words represented by switch states)
Ic (interconnect)	Bus protocols, memory controllers	Mm (addressable memory via bus addresses)
St (storage)	Memory technology (SRAM/DRAM/Flash)	Mm (memory capacity and hierarchy)
Os (oscillator)	Clock tree, PLL, timing closure	Cy (instruction cycle timing)
Pt (port)	I/O controllers, PHY chips, protocol engines	Ch (communication channels)
Pw (power)	Voltage regulators, power management ICs	(ambient at computing level — power assumed)

Power (Pw) becomes AMBIENT at the digital computing level — computing assumes power without making it an explicit primitive. This parallels how Entity system's X (Execution) becomes ambient at the app architecture level.

Step 12 — Manifestation Landscape

Positioned systems

System	Sw	Ic	St	Os	Pw	Pt
Single transistor	1	0	0	0	0	0
555 timer IC	2	1	1	2 (self-oscillating)	1	1
Arduino ATmega328	3 (8-bit MCU)	2 (on-chip bus)	2 (SRAM+Flash)	2 (clock dist)	1 (regulated)	2 (GPIO)
Raspberry Pi BCM2711	4 (quad-core ARM)	3 (hierarchical)	3 (LPDDR4)	3 (PLL)	2 (multi-rail)	3 (USB, Ethernet, GPIO)
Intel Core i9	4 (x86 cores)	4 (ring bus + mesh)	3 (cache hierarchy)	4 (multi-domain, DVFS)	4 (per-core VR)	4 (PCIe, DDR5)
NVIDIA H100 GPU	4 (streaming multiprocessors)	4 (NVLink, HBM interconnect)	3 (HBM3)	3 (warp scheduler)	3 (multi-rail)	4 (PCIe, NVLink, NVSwitch)
Apple M3 SoC	Full (CPU+GPU+NPU integrated)	4 (unified memory architecture)	3 (unified LPDDR5)	Full (DVFS per cluster)	4 (advanced power management)	4 (Thunderbolt, WiFi, Bluetooth)
Xilinx FPGA	Full (reconfigurable)	3 (programmable interconnect)	2 (block RAM + DDR interface)	3 (multi-clock domain)	2	3 (configurable I/O)
ESP32 (IoT)	3 (dual-core)	2	2 (SRAM+Flash)	2	2	Full (WiFi, Bluetooth, GPIO, ADC — many interfaces)
Vacuum tube flip-flop (1940s)	1 (tubes)	1 (point-to-point)	1 (tube-based latch)	0-1	0 (unregulated)	1 (wired terminals)

What the landscape reveals

The Sw axis tracks Moore's Law: Sw1 (discrete) → Sw2 (IC) → Sw3 (LSI) → Sw4 (processor) → Sw-Full (reconfigurable). The history of hardware IS the history of switch integration.

Apple M3 at highest integration: Full Sw (heterogeneous processors), Full Os (DVFS), high across everything. This IS what "system on chip" means — maximum integration of all hardware primitives on one die.

FPGA is Sw-Full but moderate elsewhere: Reconfigurable switches are the MOST advanced switch technology, but FPGA memory and power management lag behind dedicated processors. The tradeoff: flexibility vs optimization.

ESP32 is Pt-Full but moderate switches: IoT chip has MANY interfaces (WiFi, Bluetooth, GPIO, ADC, DAC, touch, I2C, SPI, UART) but moderate processing power. The chip exists to INTERFACE, not to compute. Perception-heavy at the hardware level.

Vacuum tube at minimum: Everything at level 0-1. Correctly positioned as the origin point of digital hardware.

Summary

Property	Value
Domain name	Physical Hardware
Primitives	6: {Sw, Ic, St, Os, Pw, Pt}
Hub	Switch (Sw) — with Power (Pw) as independent root
Core triad	{Sw, Ic, St} — sequential digital circuit
Filter	22/64 = 34.4%
Heavy pairs	7/15 = 47%
Dependency depth	2 (shallow — two-root structure)
Genesis transition	Sw1→Sw2 (integrated circuit — switches on silicon)
Two-root structure	Sw (logic) + Pw (energy) — mirrors SSA's En+Cx and app arch's D+Pc
Key finding	Power (Pw) becomes AMBIENT at digital computing level — same pattern as X becoming ambient at app level

Referenced by the model

Cited as a source by 1 model record (browse the model census):

physical-hardware — domain entity/sc1